The present invention relates to forward error correction synchronization. In telecommunication, information theory, and coding theory, forward error correction (FEC) or channel coding is a technique used for controlling errors in data transmission over high speed, unreliable, or noisy communication channels.
For example, in 32 Gigabit Fiber Channel transmission links, FEC hardware logic is added to a network stack of components receiving and transmitting data. The transmission includes a data stream that is partitioned into multiple code words. The FEC hardware may calculate and insert a checksum after each transmitted code word. In the 32 Gigabit Fiber Channel implementation a code word may be 5280 bits long including 5140 bits for the code words and 140 bits for a checksum portion. On a receive side, FEC hardware logic processes a complete code word and can use the data in the checksum portion to correct a certain amount of errors in the code word. The receive side may need to identify a starting point of the multiple code words. If the FEC hardware logic identifies a starting bit position in which the amount of errors in a given code word equals zero, and a subsequent code word contains no errors, the starting bit position may be identified as the correct starting position. In 32 Gigabit Fiber Channel, identifying the starting point may be done by processing each FEC code word at each possible starting position in the data stream. In other words, the FEC hardware logic may be required to attempt processing of the FEC code words at each of the 5280 bits.